Conventional architectures for digital electronic systems, such systems including data processing systems such as computers, as well as control systems, communication systems, and the like, communicate information between integrated circuit components by way of "buses". Buses are transmission lines, generally configured as a metal line on a printed circuit board, but which also may be implemented as a conductive (e.g., metal or doped semiconductor) line within an integrated circuit chip, and to which various circuit functions are connected in such architectures. These circuit functions are capable of driving the bus with digital information, receiving digital information from the bus, or both, such digital information corresponding to data, address values, control signals, and the like.
Where multiple driver circuits are connected to the same bus, the system must be controlled in such a manner to prevent two or more drivers from simultaneously driving the bus with complementary data states for significant periods of time. Conflicting data states on a bus can result in excessive power dissipation, and damage to the driver circuits in the electronic system. Conventional electronic circuits thus generally include drivers which are capable of presenting a high impedance at their outputs, so that the buses connected thereto may be released, and data driven thereupon from another circuit. As is well-known, such drivers are commonly referred to as "tristate" drivers, and the buses referred to in the system context as "tristate" buses.
Referring to FIG. 1, a portion of a conventional electronic system is illustrated relative to a single bus line BUS.sub.n. Line BUS.sub.n is but a single data line of a bus; modern buses in data processing systems now include up to as many as thirty-two such lines for the simultaneous communication of a thirty-two bit digital word. Connected to bus line BUS.sub.n are integrated circuit components 2.sub.0 through 2.sub.3, each capable of performing an electronic function in communication with bus line BUS.sub.n to which each is connected. Generally, each of integrated circuits 2 will have a terminal connected to each of the lines in the bus; for example, for a sixteen bit bus, integrated circuit 2.sub.0 would have sixteen terminals, each connected to a different one of the bus lines. Such parallel connection is not shown, for purposes of clarity.
Integrated circuits 2 correspond to different electronic functions, and thus may connect to bus line BUS.sub.n in varying fashion. For example, integrated circuit 2.sub.0 may be a data processing device such as a microprocessor or a custom integrated circuit (e.g., an application specific integrated circuit, or ASIC) which receives data from bus line BUS.sub.n, processes the data according to a program or algorithm, and presents the results back onto bus line BUS.sub.n. As such, integrated circuit 2.sub.0 includes a bidirectional input/output circuit I/O therewithin which both receives and presents data onto bus line BUS.sub.n. In contrast, integrated circuit 2.sub.1 may be a read/write memory, such as a RAM, which is written by data on bus line BUS.sub.n and which, in a read operation, presents data onto bus line BUS.sub.n. Integrated circuit 2.sub.1 thus also has both an input and an output coupled to bus line BUS.sub.n, by way of a bidirectional input/output circuit I/O; alternatively, dedicated input and output terminals (and associated receiver and driver circuits, respectively) may be provided in integrated circuit 2.sub.1. Integrated circuit 2.sub.2 may be an input device, read-only memory, or a similar function which only presents data to bus line BUS.sub.n, and accordingly includes an output circuit Q connected thereto. Conversely, integrated circuit 2.sub.3 may be an output device, such as a display or printer driver function, and as such receives data from bus line BUS.sub.n via input circuit I.
Other similar architectures are, of course, well known in the art. For example, bus line BUS.sub.n may be a serial bus, in which it would be the only bus line in the bus. In addition, for either a parallel or serial bus, integrated circuits 2 may be individual circuit functions in a VLSI integrated circuit, such as a microprocessor, which is designed according to a bus architecture. In addition, the selection and arrangement of particular circuit functions coupled to a common bus line BUS.sub.n is unlimited.
As noted hereinabove, where bus line BUS.sub.n is a tristate bus line, some type of control is necessary so that no two circuits 2 are simultaneously driving bus line BUS.sub.n with conflicting digital data states, for significant periods of time. A first conventional technique for achieving such control is to ensure, in the operation of the system, that all output drivers coupled to bus line BUS.sub.n are in a high-impedance state before enabling an output driver in any one of circuits 2 to drive the bus. While such a scheme avoids bus contention and conflict, and avoids the dissipation of current which can result from such conflict even for a short period of time, certain problems can arise from this scheme. A first problem is that bus line BUS.sub.n, with all drivers in high-impedance, will float to an indeterminate voltage due to coupling of noise through unavoidable parasitic impedances, and to other causes. If the voltage to which bus line BUS.sub.n floats is near the trip point of one or more receivers coupled thereto, significant current can be drawn through the receivers. In addition, false switching of the receivers can occur if bus line BUS.sub.n floats past a receiver trip point. Accordingly, it is generally undesirable to allow a nondriven bus line BUS.sub.n to float to an indeterminate voltage.
Another technique used in the system context of FIG. 1 to prevent both significant bus contention and bus floating is to control integrated circuits 2 in such a manner that driving of the bus overlaps for a brief time. This is accomplished by maintaining one of the output drivers in a circuit 2 in an active state until just immediately after an output driver in another circuit 2 begins to drive the bus; in this way, bus line BUS.sub.n is never left to float. However, during such time as the two drivers are both on, with conflicting data states, the power dissipation can be quite large. Such large power dissipation will of course damage the circuits if maintained for sufficient time, but even for brief pulses can generate system noise, glitches on the power supplies, and indeterminate operation of receivers connected to the bus.
Passive techniques for maintaining the data state of a bus have also been used. Referring now to FIGS. 2a and 2b, two conventional receiver circuits 4a, 4b, are illustrated which include such passive control of the output. Receivers 4a, 4b are each for communicating data from node IOEXT to node IOINT. In this example node IOEXT is for coupling to a bus line, such as bus line BUS.sub.n of FIG. 1, and node IOINT is for coupling to an internal node of the integrated circuit which includes receiver 4a or 4b. Receivers 4a, 4b each include p-channel transistor 6p and n-channel transistor 6n connected in conventional CMOS inverter fashion, having their source-drain paths connected in series between power supply voltage V.sub.cc and ground, and having their gates coupled in common to node IOEXT; the output of the inverter is at the common drain node. The common drains of transistors 6 are coupled to the common gates of p-channel transistor 10p and n-channel transistor 10n, also connected in CMOS inverter fashion, and which have their drains connected in common at node IOINT. Receiver 4a, 4b each further include p-channel transistor 8p and n-channel transistor 8n, coupled as a CMOS inverter, with their common gates coupled to node IOINT and their common drains coupled to the gates of transistors 10 and the drains of transistors 6.
In operation, each of receivers 4a, 4b receive a logic state at node IOEXT which it logically inverts twice by way of the inverter of transistors 6 and the inverter of transistors 10, with one of transistors 10p, 10n driving node IOINT with the received logic state. The driven data state is latched at the gates of transistors 10 by the inverter of transistors 8, so that the data state at node IOINT is latched and maintained even if the bus line to which node IOEXT is coupled is later taken to a high impedance state.
Conventional receiver 4a further includes p-channel transistor 12p which is implemented in order to keep system bus lines BUS.sub.n, to which node IOEXT is connected, from floating. P-channel transistor 12p has its drain coupled to node IOEXT, and has its source biased to the V.sub.cc power supply; the gate of transistor 12p is coupled to ground, so that transistor 12p is always on. In effect, transistor 12p is a pull-up resistor; a transistor having a fixed gate voltage is generally more easily implemented in modern integrated circuit processing than a diffused or polysilicon resistor. As a result, if bus line BUS.sub.n to which node IOEXT in receiver 4a does not have a logic state driven thereon by an output driver circuit, transistor 12p will pull node IOEXT and bus line BUS.sub.n toward V.sub.cc. The pull-up function of transistor 12p thus keeps bus line BUS.sub.n away from indeterminate levels near the trip point of receivers (including receiver 4a), and avoids the floating bus problems noted hereinabove.
Receiver 4b in FIG. 2b conversely includes transistor 12n, which is an n-channel transistor having its drain coupled to node IOEXT, its source connected to ground, and its gate coupled to V.sub.cc so that transistor 12n is always on. Transistor 12n thus serves as a pull-down device, and will pull node IOEXT and bus line BUS.sub.n to which it is connected to ground, similarly keeping bus line BUS.sub.n from floating to a level near the trip point of a receiver such as receiver 4b.
In either case, pull-up transistor 12p, pull-down transistor 12n, or resistors similarly connected, each keep bus lines BUS.sub.n from floating to undesired metastable voltages. However, during such time as an output driver is driving the bus line BUS.sub.n to the data state opposite from that to which the transistor 12 (or resistor) is pulling the line, DC current will be drawn and power will be dissipated. While the characteristics of transistors 12 can be selected by way of layout to reduce the power dissipation, DC power is still necessarily drawn for such opposing data states. In addition, transistors 12 add load to the output driver circuits, reducing system performance and requiring additional drive capability for such circuits.
Alternative pull-up and pull-down schemes for keeping bus lines BUS.sub.n from floating include the use of pull-up or pull-down devices in combination with open-drain (or open-collector) output driver circuits; similarly as noted hereinabove, an opposing data state will cause DC current to be drawn through the pull-up or pull-down device. Yet another scheme uses both a pull-up and a pull-down device to keep bus line BUS.sub.n at a selected voltage near a receiver trip point to reduce the DC current when the bus is driven, but far enough away from the trip point to avoid false switching when the bus is in tristate. While the DC current is reduced by this arrangement, such current is drawn regardless of the data state driven on the bus line, as either the pull-up or the pull-down device is opposed by the driven data state.
In recent years, battery powered electronic systems have become more desirable and achievable, particularly with the advent of high speed CMOS technology. Examples of such battery powered systems include laptop or notebook-sized personal computers, as well as portable digital instrumentation, and portable digital entertainment systems (e.g., CD players). In order for battery life to be acceptable to the user of such systems, DC current drawn by the system must be minimized. The bus control schemes noted hereinabove which incorporate pull-up or pull-down devices each achieve such control at the expense of DC power dissipation. Such power dissipation, particularly as more functions are coupled to a given bus, may not be tolerable in a battery powered system.
It is therefore an object of this invention to provide a receiver circuit which includes keeper circuitry for controlling a tristate bus line in the high impedance state, at very lower power dissipation levels.
It is a further object of this invention to provide such a receiver circuit which can be readily implemented by conventional fabrication technology.
It is a further object of this invention to provide such a receiver circuit which is suitable for use in a bidirectional I/O cell for an application specific integrated circuit.
It is a further object of this invention to provide such a receiver circuit which can be used for interchip or intrachip bus control.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.